The present invention relates to an oscillation circuit for oscillatory operations utilizing the charging and discharging function of a capacitor.
Various types of oscillation circuits have been conventionally proposed. For example, FIG. 1 shows one example of a well known conventional CR oscillation circuit. This oscillation circuit has an amplifier 2 for amplification of a voltage applied between a power source terminal V.sub.D and ground, a p- channel MOS transistor 4 whose current path is coupled between the power source terminal V.sub.D and the input terminal of the amplifier 2 and whose gate is coupled to the output terminal of the amplifier 2, a resistor 6 connected between the input terminal of the amplifier 2 and ground, and a capacitor 8 connected in parallel with the resistor 6.
Assume that an output signal of low level is generated at an output termimnal OT of the oscillation circuit shown in FIG. 1. In this case, the MOS transistor 4 is rendered conductive and the capacitor 8 is charged to the power source voltage level. The charging voltage of this capacitor 8 is amplified by the amplifier 2, and a voltage of high level is generated at the output terminal OT. Then, the MOS transistor 4 is rendered nonconductive and the charge stored on the capacitor 8 is discharged through the resistor 6. When the capacitor 8 is completely discharged, the input signal to the amplifier 2 becomes low level and an output signal of low level is generated again at the output terminal OT.
An oscillation output signal as shown in FIG. 2A is generated in this manner at the output terminal OT of the oscillation circuit shown in FIG. 1. When the voltage applied to the power source terminal V.sub.D is constant, the frequency of the oscillation output signal shown in FIG. 2A is constant since it is determined by the time constant which is defined by the resistor 6 and the capacitor 8. When the voltage applied to the power source terminal VD is low and the output signal of high level from the amplifier 2 is applied to the gate of the MOS transistor 4, the MOS transistor 4 has a large resistance of finite value. Thus, a small amount of charge is discharged from the power source terminal V.sub.D through the MOS transistor 4 and it takes a long time to completely discharge the charge on the capacitor 8 through the resistor 6.
When the MOS transistor 4 is rendered conductive by the output signal of low level from the amplifier 2, it takes a long time to charge the capacitor 8 to a predetermined level since the voltage applied to the power source terminal V.sub.D is low. When a voltage of low level is thus applied from the power source terminal V.sub.D, an oscillation output signal of a lower frequency as shown in FIG. 2B is obtained.
To the contrary, when a higher voltage is applied from the power source V.sub.D, the charging and discharging of the capacitor 8 is performed in a shorter period of time. In this case, an oscillation output signal of a higher frequency as shown in FIG. 2C is generated from the oscillation circuit.
The CR oscillation circuit shown in FIG. 1 is defective in that changes in the power source voltage V.sub.D results in changes in the oscillation frequency.
FIG. 3 shows another example of a conventional CR oscillation circuit. This oscillation circuit has three CMOS inverters 10, 12 and 14 connected in series. The CMOS inverter 10 includes, a p- channel MOS transistor 10P and an n- channel MOS transistor 10N which are connected in series between the power source terminal V.sub.D and ground. The CMOS inverter 12 includes a p- channel MOS transistor 12P and an n- channel MOS transistor 12N. The CMOS inverter 14 includes a p- channel MOS transistor 14P and an n- channel MOS transistor 14N. The output terminals of the CMOS inverters 14 and 12 are coupled to the input terminal of the CMOS inverter 10 respectively through a resistor 16 and a capacitor 18.
Assume now that the input signal to the CMOS inverter 10 changes to have a high level at a time t1 as shown in FIG. 4A for the oscillation circuit shown in FIG. 3. In this case, the MOS transistors 10P and 10N are rendered nonconductive and conductive, respectively, and a signal of low level as shown in FIG. 4B is generated from the CMOS inverter 10. In response to the output signal of low level from the CMOS inverter 10, the MOS transistors 12P and 12N are rendered conductive and nonconductive, respectively, and an output signal of high level as shown in FIG. 4C is generated from the CMOS inverter 12.
In response to the output signal of high level from the CMOS inverter 12, the MOS transistors 14P and 14N are rendered nonconductive and conductive, respectively, and an output signal of low level as shown in FIG. 4D is generated from the CMOS inverter 14. Under this condition, a discharging current flows through the MOS transistor 12P, the capacitor 8, the resistor 16 and the MOS transistor 14N and gradually decreases the level of the input signal to the CMOS inverter 10.
Thereafter, when the level of this input signal becomes lower than a circuit threshold voltage V.sub.TH of the CMOS inverter 10 at a time t2, the MOS transistors 10P and 10N are rendered conductive and nonconductive, respectively. Then, output signals of high, low and high levels as shown in FIGS. 4B, 4C and 4D are generated from the CMOS inverters 10, 12 and 14, respectively. Furthermore, since the MOS transistor 12N is conductive, the electrode of the capacitor 18 to which the power source voltage V.sub.D has been applied is forced to have a ground potential. The level of the input signal to the CMOS inverter 10 is instantaneously dropped from the level V.sub.TH to (-V.sub.D +V.sub.TH). Under this condition, a charging current flows through the MOS transistor 14P, the resistor 16, the capacitor 18, and the MOS transistor 12N. The capacitor 18 is thus gradually charged. When the level of the input signal to the CMOS inverter 10 becomes greater than the circuit threshold voltage V.sub.TH at a time t3 as shown in FIG. 4A, the MOS transistors 10P and 10N are rendered nonconductive and conductive, respectively.
In this case, since the MOS transistor 12P is rendered conductive, the power source voltage V.sub.D is applied to the electrode of the capacitor 18 which has been held at the ground potential. The level of the input voltage to the CMOS inverter 10 is raised from the level V.sub.TH to the level (-V.sub.D +V.sub.TH), and the operation as described above is repeated. An oscillation output signal as shown in FIG. 4D is generated at the output terminal OT of the oscillation circuit. Although the frequency of the oscillation output signal is determined by the time constant which is in turn defined by the resistor 16 and the capacitor 18, the frequency of the oscillation circuit also changes with variation in the power source voltage VD, as in the case of the oscillation circuit shown in FIG. 1.